A New Input Grouping and Sharing Method to Design Low Complexity FFT Implementation

FFT is a commonly applied algorithm in digital signal processing and communications. In this brief, a new low power and low complexity FFT architecture design is proposed. An input grouping method is used to reduce the multiplications of the inputs and FFT twiddle factor coefficients. In addition, a new input partial sum sharing scheme is proposed to reuse the hardware resources to further reduce the adder cost. Logic synthesis results in ASIC show that the proposed 16-point FFT architecture can save area and power cost by at least 19.1% and 19.0% respectively compared with the recently published designs. Similarly, the proposed 32-point FFT architecture can reduce both power and delay by at least 6.91% and 5.35%.