Cu barrier/seed technology development for sub-0.10 micron copper chips

Advanced PVD technologies have been reviewed for copper barrier-seed applications for different device nodes. Each new device generation requires improved step coverage and reduced overhang. With each shift in deposition technology, there have been process and hardware advancements to meet decreasing feature sizes and increasing aspect ratios. The extension of PVD to 0.1 /spl mu/m has delayed the need for a CVD barrier and seed solution. However, PVD's limitations in step coverage, and the introduction of porous low-k dielectrics may necessitate a transition to CVD barriers below 0.10 /spl mu/m. The process integration of SIP-Cu and a proven barrier solution TDMAT (tetrakis dimethyl amino titanium)-based CVD TiSiN is also discussed in this paper.