High-k gate dielectrics for sub-100 nm CMOS technology

In this paper, the materials and processing challenges for the fabrication of high-quality. ultra-thin (EOT<1 run) high-K gate stack for sub-100 nm CMOS technology are reviewed along with our recent results on CVD HfO/sub 2/. The requirement for ultra thin and robust interface layers to avoid any thickness increase due to post-deposition processing to achieve thinnest EOT are discussed. Results are presented on thermal stability of high-K materials, and interfacial reactions of high-K/Si and high-K/gate electrode. We also discuss key factors that govern the conduction and degradation mechanisms in the high-K gate stack. Both poly-Si and metal nitrides are explored as possible gate electrode materials arid the upper thermal budget limit for such materials are discussed.