Source engineering on Oxygen-Inserted Si channel for gate length scaling of low-voltage switch devices

Source engineering for gate length scaling of low-voltage power switch devices was demonstrated by shrinking baseline 5V analog MOSFETs down to 0.25um, leading to 100% increase in drive current compared to baseline devices and hence significantly lower R
SP
for both NMOS and PMOS switch devices while maintaining good SOA (safe operating area). The key source engineering concepts consist of 1) implementation of shallow junction process of core logic device; 2) halo optimization; and 3) shallow p-body layer for SOA improvement. The use of an OI (oxygen-inserted) Si channel enhances performance via carrier mobility improvement and precise doping profile control.