Substrate and Trench Design for GaN-on-EBUS Power IC Platform Considering Output Capacitance and Isolation between High-side and Low-side Transistors

A GaN on engineered bulk silicon (GaN-on-EUBS) power IC platform has been demonstrated to create isolation between high-side (HS) and low-side (LS) p-GaN gate HEMTs by implementing embedded PN junctions and deep trenches in a bulk Si substrate using mature Si-compatible processes. The design of the bulk Si substrate with respect to the doping concentration and the backside termination scheme is expected to impact on the output capacitance (C
OSS
) and the isolation capability. In this paper, we report a comprehensive study of the PN junction design in Si substrate. The physical dimensions of the trench around each power device are investigated considering the isolation and reliability of the EBUS substrate.