Edge Termination and Peripheral Designs for SiC High-Voltage (HV) Lateral MOSFETs for Power IC Technology

This paper focuses on the demonstration of various design architectures (edge termination and peripheral designs) of the lateral HV nMOSFETs fabricated on a 6" N-epi/N+substrate and N-epi/P-epi/N+substrate for the development of HV SiC Power ICs. Along with the cell design, the peripheral design of the lateral HV nMOSFET plays a significant role in attaining an optimum breakdown voltage by effective termination of the electric field. Furthermore, the peripheral design also considerably determines the footprint of lateral HV power MOSFET for power IC integration. The lateral HV MOSFETs reported in this work are one of the best in class with the superior BV-R
on,sp
trade-off, and also with high current handling capability.