Optimisation of the carrier lifetime profile in 1.2kV planar and trench SiC MOSFETs

This paper presents a comprehensive study on the optimisation of the lifetime profile in the drift region of 1.2kV planar and trench 4H-SiC MOSFETs. The performance of the body diodes is examined for the first time for a range of single step lifetime profiles in the epi region by means of a dedicated TCAD model, thereby enabling the identification of a trade-off between the voltage drop, the reverse recovery, and the risk of forward bias degradation. Based on this, a set of buffer designs is investigated as a means of containing bipolar degradation and hence loosening this trade-off.