Modeling of In-chip Current-Temperature Distribution of SiC Power MOSFETs during Fast Switching Events

This paper presents a modeling approach that allows the prediction of both current and temperature distribution within a SiC MOSFET die during a fast switching event in Spice circuit simulations. It is based on an equivalent model developed including the 3-D gate layout parasitics and a 3-D R-C network for the thermal die model. The gate layout parasitics are modeled by an analytical R-L model extracted from a 3-D layout geometry, so that not only resistive but also inductive effects are taken into account. Accordingly, the computational complexity is reduced compared to the electromagnetic (EM) models extracted from 3-D EM tools, which is highly important for computational efficiency of circuit simulations with thousands of SiC power MOSFET instances. Furthermore, the proposed modeling approach enables multi-objective analysis of the gate layout design for optimized device performance with respect to the switching and conduction operation modes.