Efficient Implementation of Dilithium Signature Scheme on FPGA SoC Platform

In the process of NIST postquantum cryptography standardization, module lattice-based Dilithium has been chosen as one of the three third-round finalists for digital signature schemes. More evaluations of its implementation efficiency on different platforms are required for further competition. In this article, we present an efficient implementation of Dilithium on a field-programmable gate array (FPGA) system-on-chip (SoC) platform. To achieve a high computation speed, we design a hardware architecture to perform the main body of the algorithm, and the preprocessing and postprocessing steps are accomplished by the processor. For the hardware architecture, we take some optimizations on the most time-consuming operations, that is, polynomial multiplication, hashing, and sampling. Polynomial multiplications are accelerated by the radix-4 number theoretic transform (NTT) architecture with a conflict-free memory mapping scheme. A fast modular multiplication on the Dilithium modulus is proposed to support the underlying calculations. For hashing and sampling, we design a multipurpose hashing unit and a compact sampling unit. The cooperative work of the two units accelerates the sampling process significantly. We implement the Key Generation, Signing, and Verification algorithms of the round-3 Dilithium at all three security levels on the Xilinx Zynq-7000 platform. Compared with existing software/hardware codesign for Dilithium on a similar platform, our design achieves about $17\times $ and $40\times $ improvements in performance for the Signing and Verification algorithms, respectively, at the cost of about $7.8\times $ more look up table (LUT) resources.