HLS Implementation of Quantum Shor’s Algorithm Using Matrix Pruning

Shor’s integer factoring algorithm served as a significant breakthrough in the field of quantum computing owing to its potential applications in modern cryptography. Simulating quantum algorithms in a way that offers a close imitation of quantum computers is required to provide some insight viably. This paper proposes an FPGA implementation of the Shor’s algorithm by employing High Level Synthesis (HLS). A detailed method of implementation including design of data-flow graphs, pruning matrices using Python scripts, writing a HLS compatible C++ code, and subsequent hardware synthesis is presented for an 8-qubit system. An estimated maximum frequency of 180 MHz has been achieved in this design.