Simulation methodology for timing analysis and design optimization in digital superconducting electronics

Rapid Single Flux Quantum (RSFQ) circuity can yield ultra-low-power high speed digital designs, but it has traditionally required specialized EDA tools for circuit simulation because of the superconducting nature of Josephson junctions. As development activity increases for the next generation of low power high performance computing, there is a need for a high-capacity circuit simulator to enable large scale design analysis for superconducting electronics (SCE). As part of the Synopsys SuperTools program, PrimeSim HSPICE has been under development for SCE since 2017, and the simulator has been enhanced to support Josephson junction devices. HSPICE brings high capacities in circuit simulation and analysis to SCE and is integrated with an advanced custom design platform. In this paper, we discuss the unique features developed for the simulator in order to support SCE design, and the simulation methodology customized for SCE circuit timing analysis and design optimization. Case studies on two RSFQ logic cells and a Josephson junction transmission line (JTL) circuit are presented as a proof of concept.