Improving SRAM Performance With Different Interconnect Options at the 7 nm Process Node

Modern-day technology node scaling trends have exacerbated interconnect resistance and capacitance problems in chips. The ultra-narrowing wires that result in higher resistance and delays impact larger wire-heavy circuits with memory components tremendously. As a result, performance enhancement is difficult at smaller technology nodes. To attempt a solution to this issue, we research alternative options that minimize interconnect and via resistances. This paper investigates how different backend-of-the-line (BEOL) options in SRAM cells affect overall chip performance and power consumption. We found that swapping the interconnect material with ruthenium yielded the greatest gains in performance, especially in read and write latency with a gain of up to 1.572x and 1.481x respectively over the current best known method. Thinning the metal barrier also provided an improvement of up to 1.425x and 1.408x in read and write latency over current methods.