Realization of a 16-bit MIPS RISC pipeline processor

Reduced Instruction Set Computer (RISC) based Pipeline architecture plays an essential role in the design of computer-based hardware embedded systems. In this paper, the internal structure of a 16-bit embedded hardware RISC processor is presented. The architectural concept was built based on the Harvard data path is comprised of five pipeline stages: fetch, decode, execute, memory, and write back. The first step of it is analyzing the data flow path inside the RISC processor which is comprised of two types of digital devices. These devices are combinational logic gates and sequential state machines. The second step is synchronizing read and write operations with the control signals generated by the control unit. All the hardware modules of the designed system are modeled using VHDL Language. The pipeline processor is simulated using the Xilinx ISE Design Suite 14.7 tool that provides a schematic view for the designed modules and facilitates the interconnection layers between the pipelined stages implemented on Spartan-3 FPGA of type XC3S200 chip.