Memory Optimized Hardware Implementation of Open FEC Encoder

This brief presents a power and memory-optimized hardware implementation for the open forward error correction (oFEC) encoder proposed for high-speed fiber optical communications. Instead of storing a large amount of previously encoded data in the memory as suggested in oFEC proposal, we propose an alternative algorithm that requires the knowledge of only a few blocks of preencoded partial parity-check bits with the goal to reduce circuit power consumption. We then present a hardware implementation architecture for both the standard and optimized encoding algorithms and demonstrate that power dissipation and area overhead are reduced multiple times by optimized implementation.