Study of Vertical Capacitance in an n-Type 4H-SiC Stepped Thick-Oxide Trench MOS Structure

In this work, characteristics of trench sidewall capacitance were investigated in a 4H-SiC stepped thick-oxide (STO) trench metal–oxide–semiconductor (MOS) structure. Multigroup SiC trench MOS capacitor test patterns with different structures and geometric parameters were designed and fabricated. From the capacitance–voltage measurements, the characteristics of the described SiC STO trench MOS were calculated and analyzed, including the thicknesses of the oxide at different locations in trench, the position of the oxide step at trench sidewall, and the flat-band voltages as well as the oxide charge densities of MOS from the upper part and lower part of oxide step at trench sidewall. Results showed that the flat-band voltages of MOS from the upper part (10.2 V) and lower part (12.5 V) of trench sidewall step had pronounced positive shifts over the ideal flat-band voltage (0.36 V), indicating a massive negative charges in the sidewall oxide film. Meanwhile, the net oxide charge density of MOS from the lower part of sidewall step (
$- 0.92\times10$
¹²
cm
$^{-2}$
) was smaller than that from the upper part (
$- 2.41\times10$
¹²
cm
$^{-2}$
), which was likely attributed to the massive shallow states in the oxide and to the poor quality of the thick-oxide film grown via chemical vapor deposition technology. The present works are providing a convenient technology to monitor the trench MOS structure by measuring the capacitance during SiC trench MOSFETs fabrication.