300 mm process integration for 0.13 /spl mu/m generation with Cu/low-k interconnect technology

Successfully transferring to a 300 mm process from a leading-edge 200 mm 0.13 /spl mu/m CMOS technology using 248 nm lithography and Cu/low-k interconnect is demonstrated in the TSMC 300 mm Pilot Line. To achieve good performance with decent throughput, a 1 to 2.5 scaling factor for process power and gas flow is applicable for CVD and dry etch. Good within wafer (WIW) gap-fill for STI and ILD is obtained. WIW thin oxide non-uniformity is less than +/-1.6% by introducing O/sub 2/ gas at the ramp down stage. An OPC model set up for the 200 mm process can be used directly in the 300 mm process with comparable WIW CD uniformity. With good poly CD uniformity from proper etch process tuning, acceptable line end shortening control for 0.10 /spl mu/m devices is shown. In Cu/low-k interconnect, good patterning integrity is achieved with no edge delamination after Cu CMP. A good yield of 880 k via chain with tight multi-level Rs and low leakage is obtained. An excellent yield of 4 metal levels 4M SRAM that is comparable to 200 mm is also achieved by this 300 mm process.