High performance single work-function tungsten gate CMOS devices for gigabit DRAM

Selective sidewall oxidation processes (SEL SWO) affect the gate poly depletion under the inversion bias condition of the NFET. The depletion was due to the poly dopant outdiffusion around the gate poly sidewall edges. To minimize the depletion, a new SEL SWO process was developed. Consequently, the use of this process resulted in an improvement of the saturation current (I/sub on/) of the NFET. Accordingly, the 110 nm electrical effective channel length (L/sub eff/) NFET and 130 nm (L/sub eff/) buried channel (BC) PFET having the I/sub on/'s of 490 and 190 /spl mu/A//spl mu/m with the off-state leakage currents (I/sub off/) of 70 and 20 pA//spl mu/m at 85/spl deg/C, respectively, were achieved with excellent long-term reliability parameters. These are the highest drive currents at fixed I/sub off/'s for the smallest gate lengths, reported to date for a DRAM technology.