Co-Optimization Between Static and Switching Characteristics of LDMOS With p-Type Trapezoidal Gate Embedded in Drift Region

In this article, a novel p-type trapezoidal gate (PTG) lateral double-diffused MOSFET (LDMOS) is proposed and investigated by the 3-D TCAD simulation. The results reveal that the PTG LDMOS boasts a reduced gate-to-drain charge (
${Q}_{\text {GD}}$
) while maintaining an acceptable breakdown voltage (BV) and specific ON-resistance (
${R}_{ \text{ON},\text {sp}}$
). Compared with conventional LDMOS, a better tradeoff between the static figure of merit (FOM
_S
, FOM
$_{\text {S}}\,\,=$
BV
²
/
${R}_{ \text{ON},\text {sp}}$
) and the dynamic figure of merit (FOM
_D
, FOM
$_{\text {D}} = {R}_{ \text{ON},\text {sp}} \cdot {Q}_{\text {GD}}$
) is realized. In the ON-state, the p-type polysilicon gate embedded in the drift region induces multiple plane majority-carrier accumulation layers, leading to a decrease in
${R}_{ \text{ON},\text {sp}}$
. In the OFF-state, the metal–insulator–semiconductor (MIS) capacitor, which is composed of extended trench gate, gradual trapezoidal oxide, and N-drift. assists in depleting the drift region. Therefore, the doping concentration of drift region can be significantly lifted, and the BV is increased. Besides, the p-n junction capacitor composed of p-type and n-type polysilicon isolates the field coupling between gate and drain, and the gate-to-drain capacitor (
${C}_{\text {GD}}$
) is thus reduced. Compared with multiple-plane electron accumulation layer LDMOS (MAL LDMOS) and split triple-gate LDMOS (STG-LDMOS),
${Q}_{\text {GD}}$
and
${R}_{ \mathrm{\scriptscriptstyle ON},\text {sp}}$
of our proposed PTG LDMOS are shrunk by 34.3% and 54.4%, respectively. In general, the proposed PTG LDMOS achieves a better tradeoff between the static and switching characteristics.