Cost Efficient Design Of Error Detection Circuit For Nano Communication

In this paper, a cost-efficient error detection circuit is designed using Quantum Dot Cellular Automata (QCA) for Nano communication with a lower number of QCA Cells. Parity generation and detection are used to ensure that the message sent to the recipient is error-free. The suggested parity generator and checker are designed with a newly designed XOR gate which has 10.9% and 68% fewer cells, respectively, than the existing designs. The area is decreased by 16% for the parity generator and 25% for the parity checker, which is better when compared with previous layouts. Due to this improved quantum cost and area, it is more accurate to use these circuits in nano communication in order to achieve more efficient, error-free data. With the use of the QCA Designer simulation tool, 4 bit and 8 bit parity generators and parity checkers are designed and verified in order to examine the correctness of the circuit so that it can be used in error detection applications in nano technology.