Improvement of Twisting and Line-Edge Roughness of 3D NAND Deep Trench Etching on Yield Enhancement : AEPM: Advanced Equipment Processes and Materials

Structural bending of deep slit trench patterns happened in the 3D NAND development. The drawback results in the circuit suffering from missed VIA connections with wordlines (WLs) and common source line (CSL), and unexpectedly high leakage current to impact device operation. Reviewing the images of physical failure analyses (PFA), the slit profile twisting that happened during plasma etching leads to worse line-edge roughness (LER) at the bottom of 12 μm-deep trench. It was also suspected that imbalanced polymer accumulated on the sidewalls of hard mask during etching enhances the electron shielding effect, which makes asymmetrical incident ions trajectory angle worsen the bottom LER. The issues mentioned in this study can be successfully eliminated by etch recipe optimization. The electrical qualification of the slit trench profile requires excellent isolation between bit-lines (BLs) and WLs with less than 1nA of leakage current.