Compact Message Permutation for a Fully Pipelined BLAKE-256/512 Accelerator

Developing a low-cost and high-performance BLAKE accelerator has recently become an attractive research trend because the BLAKE algorithm is important in widespread applications, such as cryptocurrencies, data security, and digital signatures. Unfortunately, the existing BLAKE circuits are limited in performance and hardware efficiency. Therefore, this paper introduces the first fully pipelined BLAKE-256/512 accelerator to improve throughput and hardware efficiency. Moreover, based on the rates of changed words in consecutive message inputs, a compact message permutation scheme is proposed to reduce the area and energy consumption of the fully pipelined BLAKE-256/512 accelerator. To achieve these goals, the compact message permutation scheme includes two novel optimization techniques: register optimization, reducing the number of registers used by over 80% compared to conventional message permutation in a theoretical evaluation, and XOR optimization, decreasing the number of XOR gates by 93.8%. An ASIC-based experiment shows that the proposed compact message permutation scheme helps reduce the area and power consumption by up to 11.35% and 21.10%, respectively, for the fully pipelined BLAKE-256 accelerator and by up to 9.86% and 20.32%, respectively, for the fully pipelined BLAKE-512 accelerator. The correctness of the compact message permutation scheme is verified on a real hardware platform (an Alveo U280 FPGA).