VLSI Architecture Design Methodology for Deep learning based Upper Limb and Lower Limb Movement Classification for Rehabilitation Application

Recently, many works have proposed an highly accurate deep learning based movement classification algorithms for the assistive technology applications. But very less importance is given for it's corresponding hardward implementation. In this paper we proposed an VLSI architecture design methodology for deep learning based movement classification for assistive technology applications. LoCoMo-Net and MyoNet are the two Deep learning based networks proposed by Gautam et al [1] [2] for upper limb and lower limb for assistive technology. The proposed architecture is capable enough to adapt both the networks. We have implemented the architecture on ZYNQ ultra-
$\text{scale} + \text{MPSoC}\ \text{zcu}102\ \text{FPGA}$
. LoCoMo-Net consumes 3.5 Watts of on chip power and MyoNet consumes 5 Watts of on chip power on the FPGA. LoCoMo-Net takes 1.876ms of time to classify the task and MyoNet takes 61.988ms of time to classify the task on FPGA.