Virtual Buffers for Exposed Datapath Architectures

The limited number of globally visible registers restricts the use of instruction-level parallelism in conventional processors. Therefore, some recent architectures expose their internal datapaths so that the compiler can make use of instructions to transfer intermediate values directly between the processing units (PUs) of the processor. Buffered exposed datapath (BED) architectures additionally use first-in-first-out (FIFO) buffers on the communication paths between the PUs to avoid unnecessary synchronizations of the PUs. However, the number of communication paths, and hence, the number of FIFO buffers in a BED architecture, grows quadratically with the number of PUs which may become prohibitive for architectures with many PUs. In this paper, we therefore propose the use of virtual buffers for BED architectures in analogy to virtual channels in networks on chips (NoCs). In particular, we present an implementation of many virtual FIFO buffers with a single combined buffer so that each PU has only a constant number of combined buffers instead of a number of virtual buffers that grows linearly with the number of PUs. Moreover, the circuit size of the combined buffers grows only linearly with their size that we can determine independently of the number of PUs. Hence, using virtual/combined buffers, we can implement BED architectures with a circuit size that scales only quasi-linearly (due to the interconnection network) with the number of PUs and the size of the combined buffers.