Compositional Fault Propagation Analysis in Embedded Systems using Abstract Interpretation

Resilience against hardware faults is a major concern for safety-critical embedded systems which has been addressed in several standards. These standards demand a systematic and thorough safety evaluation, especially for the highest safety levels. In order to provide the data for this evaluation, we propose a scalable and formal approach to fault propagation analysis for hardware/software systems. We consider soft errors by single event upsets (SEUs) which corrupt data in hardware registers and examine their effect on the high-level software. Our method identifies all faults of a given fault list that can have an effect on selected objects of the high-level software, such as the specified safety functions, and gives formal guarantees for other faults that do not do any harm. Scalability of our approach results from combining an analysis at the binary and hardware level with an analysis of the high-level source code using Abstract Interpretation. The result is a mapping between a fault in the hardware and affected locations in the source code. Effectiveness and scalability of this method are demonstrated on an industry-oriented software system with about 138 k lines of C code.