FPGA Implementation of Multibit LFSR as Key Generator for AES Encryption

The changing technology and urge for betterment of lifestyles. The innovation and creation is necessary part for acquiring the needed development. The main concerns in today is to provide an efficient system or devices which can withstand all the latest cyber threats and hacks. The latest test pattern generatores which can only provide one pattern at a single clock cycle. So it creates delay while testing a huge system for fault coverage. Reducing the time for testing a system has become a prime factor in case of BIST. SO in this paper a design is proposed which can produce multiple bits at a single clock cycle. This design can reduce the time consumed to generate random patterns. In addition as an application to implement an efficient cryptography system, The system should be tested to its maximum potential and it should be prevented from external interventions. In this paper the focus is on the implementation of a Multi-bit LFSR as a key generator for AES encryption. The Multi-bit LFSR is implemented in such a way that it is useful as a test-pattern generator in logic BIST to maximize the efficiency while testing the system.The influence of Logic BIST put forwards the significance of LFSR. The LFSR provides the patterns which are used to test the system. So, implementing an LFSR which can produce more efficient patterns will help in testing a system to its maximum potential and achieve good fault coverage for the circuit. The comparison of conventional LFSR is done with implemented Multi-bit LFSR to study the advantage. And as an application in the filed of cryptography, in this paper a encryption method is proposed with Multi-bit LFSR as a key generator for AES encryption standards. The implementation is carried out in Xilinx Vivado Tool. A spartan 7 FPGA board is used for the implementations to study the characteristics and utilization