Addressing Resiliency of In-Memory Floating Point Computation

In-memory computing (IMC) can eliminate data movement between processor and memory, which is a barrier to the energy efficiency and performance in von Neumann computing. Due to low power consumption, fast operation, and tiny footprint in crossbar architecture, resistive RAM (RRAM) is one of the most promising devices for IMC applications. We present FPCAS, a pipelined floating point (FP) arithmetic (addition/ subtraction) solver based on RRAM crossbars. Although promis- ing, RRAM-based computing may experience random failures, such as the stuck-at fault where RRAM cells are stuck at either a high-resistance state (HRS), i.e., stuck-at-0 (SA0), or a low-resistance state (LRS), i.e., stuck-at-1 (SA1). We propose techniques to prevent SA1 failures, namely, shifting-at-the-output (SATO), force to $V_{\mathrm{ DD}}$ (FTV), and force to ground (FTG) since 96% of the RRAMs employed in our architecture are in HRS. Using an extra clock cycle, both strategies employ the memory array’s fault-free RRAMs to conduct the computation. When the failure rate is less than 2%, SATO can manage more than 70% of faults, whereas FTV can handle more than 90% of faults at low power and low area overhead. Simulation results reveal that, for $\mathrm{\scriptstyle NAND}$ – $\mathrm{\scriptstyle NAND}$ - and $\mathrm{\scriptstyle NOR}$ – $\mathrm{\scriptstyle NOR}$ -based implementations, FPCAS consumes 335 and 322 pJ, respectively. Both implementations incur a performance overhead of 50% at the array level and 4% for pipelined FP implementation.