On the Single Event Upset Vulnerability and Mitigation of Binarized Neural Networks on FPGAs

Binarised neural networks (BNNs) have attracted research interest for embedded deep learning applications. BNNs are well suited to FPGA implementation since BNNs have small memory utilisations and make use of many binary logic operations in parallel. Moreover, the FPGA acceleration of BNNs has very high energy efficiency and performance [1] , making FPGA-based BNNs attractive for implementing neural network capability in power-constrained satellite systems.