An Analog-Assisted Digital LDO With Dynamic-Biasing Asynchronous Comparator

This paper presents a digital low-dropout regulator (DLDO) with three-level switching (TLS) and analog-assisted (AA) structure formed by dynamic-biasing asynchronous comparator, capacitive-coupling RC network and auxiliary power switch. The proposed AA-DLDO is fabricated in a 65-nm CMOS process. The minimum load current is 18 $\mu \text{A}$ . The maximum undershoot is 200 mV under load transient of 4.82-mA/1-ns. The recovery time is 8 ns. The figure-of-merit of proposed design is better than the other DLDOs by more than 14 times.