Design of an All-Digital Phase-locked loop in a 130nm CMOS Process using open-source tools

In this paper, an implementation of an ‘All-Digital Phase-Locked Loop’ has been elucidated, which includes the RTL level synthesis of the design, and the GDS level synthesis, obtained from the RTL to GDSII flow. The implemented design consists of a Phase Frequency Detector, a K-Counter, a Digital Controlled Oscillator, with a Divide by N Counter in a feedback loop. These individual components were realized using Verilog Hardware Description Language, and an appropriate testbench was written to view the waveforms and check for their correctness using GTKWave. Later, the RTL Level Design of this implementation was obtained. and, the RTL to GDSII Flow was initialized. The tool used for executing this process is OpenLane, which is an open-sourced, automated RTL to GDSII flow based on several components like OpenRoad, Yosys, Magic, Klayout, etc. The different stages of the RTL to GDSII Flow such as Floorplanning, Placement, CTS, and Routing were performed, and the GDS and LEF files were obtained successfully. The Gate Level Simulation was done for the post-layout stage, by obtaining the synthesized design from the layout stage. The obtained GDSII file is incorporated with the open-source Sky130 Process Design Kit and can be sent to foundries that fabricate 130 nm CMOS Processes.