An UWB 18.5 GS/s Sampling Front-End with 35 dB SNDR at 39 GHz Input Frequency in 22 nm FDSOI

This paper presents the design and implementation of an ultra-wideband buffered front-end sampler (T &H) operating at 18.5 GS/
$s$
with 44 GHz measured signal bandwidth. The highly-linear sampler, intended for a 5-bit 4X time-interleaved (TI) 74 GS/
$s$
flash ADC, is realized in a 22 nm FD-SOI (FDX) CMOS process. It comprises an ultra-low jitter limiting clock path and a source-follower based T&H architecture maximizing the overall linearity and isolation as well as enhancing the effective sampling bandwidth. The front-end takes advantage of the flipped-well forward-biasing process option lowing the transistor threshold voltage by approximately 85 m V /V to achieve a differential input range of 600
$\text{mV}_{\text{ppd}}$
while using a dual 1.2 V and 0.9 V supply voltage. Characterization results reveal an SFDR and SNDR of better than 37.2 dBc and 35 dB (ENOB=5.5 bits) respectively using a single-tone sine wave in the fifth Nyquist zone
$(\mathrm{f}_{\text{in}}=39$
G Hz) and an SFDR of 40.9 dBc with a wideband two-tone input at
$\mathrm{f}_{\text{in}1}=1.5$
G Hz and
$\mathrm{f}_{\text{in}2}=36.1$
G Hz. The compact front-end design with the input buffer, T &H core, clock buffer and low jitter sample-phase generator occupies a core are of as small as 0.004 mm2 in the utilized 22nm FD-SOI process. The total power consumption is only 75mW of which 10mW is consumed by the entire clock path operating from the 0.9V supply.