TLM-NoC: Two Level Mesh Network-on-Chip for Performance Improvement

As the number of cores integrated into a system-on-chip (SoC) increases, the role played by this on-chip communication system becomes more and more critical due to communication bottleneck and scalability. The network-on-chip (NoC) design paradigm is today recognized as the most viable communication infrastructure over SoCs. However, the former architecture imposes latency concerns while the network size increases resulting in significant performance degradation. This paper finds an alternative solution for improving mesh NoCs, especially when long-distance communication takes place. The proposed solution suggests a variant of the 2D mesh topology named “two-level mesh - network-on-chip (TLM-NoC)” in which a baseline mesh includes sparse mesh interconnection at the upper layer. The upper layer primarily establishes long-distance communications between nodes which in turn reduces latency and improves other metrics. Experimental results show adequate performance improvements by the TLM-NoC over traditional meshes. Evaluation of TLM-NoC shows latency improvement by 17.97%, resulting in 33.33% packet flit loss reduction and 26.80 % increased throughput. Further, the proposed architecture consumes 23.69% less energy for delivering traffic.