Experimental Investigation of Charge Sharing Induced SET Depending on Transistors in Abutted Rows in 65 nm Bulk CMOS Technology

The effect of transistors in abutted rows on charge sharing is investigated by changing the configuration of the transistors in abutted rows in this work. 3D TCAD numerical simulations indicate that the existence of transistors in abutted rows can mitigate the occurring probability of charge sharing, especially charge sharing induced by ion striking at the vicinity of n-well contact. The simulations also indicate that the single event double transient (SEDT) pulse width is reduced obviously by the transistors in abutted rows for ion strike location near n-well contact. A 65 nm test chip was designed in commercial 65 nm twin-well bulk CMOS process, and heavy-ion experiment was conducted. The experiment results agree well with the simulation results, which indicates that the effect of transistors in abutted rows on single event sensitivity and the occurring probability of charge sharing is more than 10%, and then considering the effect of transistors in abutted rows is necessary in nanometer technology.