Optimized methods on comparator design

This paper introduces four types of optimization methods on comparators to improve its performance. The first comparator adopts a triple-latch feedforward design, performing a much lower delay less than 26.8ps. It dissipates 2.2mW at 13.5Gb/s, holding a wide common mode and supply range in less than 70ps delay. Compared to the conventional version with an offset standard deviation of only 2.05mV, the second one improves the speed of the comparator by adding additional parallel paths to the output node, which increases around 50% speed. The third comparator uses a PMOS transistor at the input of the preamplifier of the comparator and the latch stage controlled by a local clock generator, which sets the optimum delay for preamplification at a 30% higher speed and decreases power consumption up to 50%. The fourth comparator presents two designs. Referred to the conventional strong-arm latch topology, the first one proposes a DB integration using a pair of tail capacitor to reach a lower input common-mode voltage and a better power efficiency. However, the design becomes infeasible in specific extreme input voltage corner. To solve the drawback, it puts forward a floating inverter pre-amplifier with reservoir capacitor, which saves seven times energy efficiency to the conventional design.