A High Speed Dynamic Logic Circuit Design with Low Propagation Delay and Leakage Current for Wide Fan-In Gates

In higher-functioning circuit applications, dynamic logic circuits are used because of their speed. However, the dynamic logic’s performance is not very promising due to its high propagation delay and high leakage current problem. A novel dynamic logic model with low leakage current and propagation delay in contrast to previous models, is developed by adding delay components and changing stacking effect circuitry. The LTSpice tool is used to illustrate the robustness of the proposed model utilizing 45nm PTM technology for the OR logic gate functionality.