Design of a Dual Processor Based Single Board GNSS Receiver Embedded Navigation Computer for Low Cost Launch Vehicles

As space sector becomes more business oriented and space-based services becomees an essential part of daily life, the access to space has to be less expensive. Conventionally MIL-883 qualified electronic components are used for the launch vehicle avionics, which is manifold costlier, bulkier and power consuming compared to industrial grade electronics. The low-cost launch vehicles with industrial grade electronics for onboard avionics systems with higher level of functional abstraction is becoming a new standard for the upcoming space vehicles. In a step towards designing and realizing low-cost unified navigation computer for GNSS receiver functions, Inertial Navigation processing and Integrated navigation functions, a single board computer is designed with industrial standard electronics. The cost of the system is reduced by selecting highly reliable industrial standard electronic components while incorporating all fault tolerant pedigree of conventional avionics systems. The navigation computer includes an RF front end for processing GNSS signals, an FPGA based GNSS correlator section, a processor for doing GNSS receiver functions, an FPGA based communication module and a second processor for doing Inertial Navigation and Integrated navigation functions. A novel Inter-processor communication scheme is designed, which ensures flawless data transfer between the processors. Necessary simulation interfaces are also designed to do ground-based hardware/processor in loop simulations. The hardware and software design, realization and integration are completed and the system is qualified for launch vehicle applications. The overall hardware and software design of the system is covered in this paper along with the Inter-processor communication scheme