Comprehending In-memory Computing Trends via Proper Benchmarking

Since its inception in 2014 [1], the modern version of in-memory computing (IMC) has become an active area of research in integrated circuit design globally for realizing artificial intelligence and machine learning workloads. Since 2018, > 40 IMC-related papers have been published in top circuit design conferences demonstrating significant reductions (>20X) in energy over their digital counterparts especially at the bank-level. Today, bank-level IMC designs have matured but it is not clear what the limiting factors are. This lack of clarity is due to multiple reasons including: 1) the conceptual complexity of IMCs due to its full-stack (devices-to-systems) nature, 2) the presence of a fundamental energy-efficiency vs. compute SNR trade-off due to its analog computations, and 3) the statistical nature of machine learning workloads. The absence of a rigorous benchmarking methodology for IMCs - a problem facing machine learning ICs in general [2] - further obfuscates the underlying trade-offs. As a result, it has become difficult to evaluate the novelty of IMC-related ideas being proposed and therefore gauge the true progress in this exciting field.