Low-Latency and Reconfigurable VLSI-Architectures for Computing Eigenvalues and Eigenvectors Using CORDIC-Based Parallel Jacobi Method

This article proposes a low-latency parallel Jacobi-method-based algorithm for computing eigenvalues and eigenvectors of
$n\times n$
-sized real-symmetric matrix. It is a coordinate rotations digital-computer (CORDIC)-based iterative algorithm that comprises multiple rotations and hence the key contribution of our work is to reduce the time cost of each rotation. Thus, alleviating the total latency for computing eigenvalues and eigenvectors using the parallel Jacobi method. Based on this proposed algorithm and additional architectural optimizations, a new low-latency and highly accurate VLSI-architecture has been presented in this manuscript for computing eigenvalues and eigenvectors of real-symmetric matrix. Subsequently, this work proposes a reconfigurable algorithm and its VLSI-architecture for computing eigenvalues and eigenvectors of complex Hermitian (CH), complex skew-Hermitian (CSH), and real skew-symmetric (RSS) matrices. Performance analysis of the proposed architectures has demonstrated minimal error-percentage of 0.0106% which is adequate for the wide range of real-time applications. The proposed architectures are hardware implemented on Zynq Ultrascale+ field-programmable gate array (FPGA)-board that consumed short latency of
$9.377~\mu \text{s}$
while operating at maximum clock frequency of 172.75 MHz. Comparison of our implementation results with the reported works showed that the proposed architecture incurs 43.75% lower latency and 89.4% better accuracy than the state-of-the-art implementation.