High-Resistivity Substrates with PN Interface Passivation in 22 nm FD-SOI

In this paper, GlobalFoundries’ 22 nm FD-SOI process was run on standard and high-resistivity wafers evaluating a PN junction interface passivation solution to counter parasitic surface conduction (PSC) effects. Substrate quality was monitored in terms of losses, effective resistivity (ρ
eff
) and generated harmonics through on-wafer measurements of coplanar waveguides (CPW), fabricated in either bottom metal or in top metal layers. The PN patterns demonstrate effective passivation of the PSC, enabling ρ
eff
values in the kΩcm range. Patterns with bias contacts were fabricated, demonstrating substantial increase in ρ
eff
when applying a reverse bias to widen the depletion regions. PN grid patterns also exhibit good RF performance results, and are attractive since they alleviate layout/PN pattern co-design.