Advanced 3d Design and Technologies for 3-Layer Smart Imager

CMOS Imagers have adopted 3D integration using Back-Side Illumination (BSI) technology, with 2 CMOS layers assembled using Wafer-to-Wafer and advanced Hybrid Bonding technology. Targeting innovative AI and Machine Learning application, for offering AI processing at the edge within the image sensor itself, this paper presents some new 3D design and technology solutions in order to build a 3-layer Smart Imager. The hybrid bonding technology for assembly of multi wafers with a capability below 1 µm pitch is shown as well as Through Silicon Via (TSV) of 2 µm pitch compatible with hybrid bonding. To offer Design Technology Co-Optimization (DTCO) capabilities, a Place & Route methodology is proposed with the associated PDKIT to benefit of fine pitch interconnects.