Investigation on selectively etched SiGe and Si surface for Gate-All-Around CMOS devices fabrication

The Si0.8Ge0.2 GAA-FET were successfully fabricated with Si GAA-FET using the same epi-layers and HKMG process for CMOS device fabrication. This study approached two selective etching processes and investigated both etched surfaces to obtain the multi-bridge channels (MBCs) for advanced SiGe p-FET and Si n-FET. The etched Si layers used in GAAFETs showed a practical on/off ratio with a subthreshold slope (SS) of 90 mV/decade. On the other hand, the etched surface of the advanced SiGe layers showed noticeable interface defects, and it was optimized by using PMA 800
^o
C/5min.