Status and challenges of in-memory computing for neural accelerators

In-memory computing (IMC) has emerged as a promising concept for neural accelerators. While the energy efficiency appears to be substantially enhanced by IMC, there are still several key challenges in terms of feasibility, reliability and maturity of IMC. This work addresses the status and challenges of IMC from a device perspective. After illustrating a reference implementation with resistive random-switching memory (RRAM), state-of-the-art emerging memories are compared in terms of conductance and its variation, which play a key role in the inference accuracy and scalability of IMC. A quantitative benchmark will be proposed by assessing throughput, area and energy efficiency for various IMC technologies.