Common-Mode Voltage Mitigation Strategies Using Sigma–Delta Modulation in Five-Phase VSIs

Various sigma–delta (
$\Sigma$
$\Delta$
) modulation techniques for reducing the maximum peak-to-peak amplitude of common-mode voltage (CMV) by 80% in a five-phase, high-frequency voltage source inverter (VSI) are proposed and evaluated in this article. These techniques are based on choosing a set of vectors that limits the CMV amplitude. Operating the VSI under high-frequency pulsewidth modulations (PWM) generates a large number of changes in the CMV levels, which leads to common-mode currents (CMCs) and conducted electromagnetic interferences (EMIs). The proposed modulation techniques achieve the following: 1) High-efficiency converter operation and output voltage with low total harmonic distortion (THD); 2) an 80% reduction in CMV peak-to-peak amplitude; 3) a decrease in the number of the CMV transitions, thus reducing the CMCs; and 4) a decrease in the conducted EMI amplitude. The use of single-loop and double-loop
$\Sigma$
$\Delta$
modulators is analyzed by means of Matlab/Simulink and PLECS simulations. The implementation of the proposed modulation techniques has been experimentally evaluated using a five-phase VSI with silicon carbide semiconductors. In order to demonstrate the improved performance, the results obtained are compared with those of other PWM and space vector modulation techniques that also mitigate the CMV amplitude by 80% but lack the other improvements.