Implementation of Scalable Non-Recursive Merge Sort on FPGA

Sorting is a classic algorithm that is fundamental building block of many algorithms. Many algorithms requiring high speed data processing nowadays are hardware accelerated using re-configurable architecture like Field Programming Gate Array (FPGA) which can outperform CPU architecture in terms of performance. Since sorting is computation-intensive operation in any algorithm, faster, efficient and scalable sorting algorithm is important to achieve hardware acceleration. In this paper, scalable non-recursive merge sort algorithm is implemented using FPGA and its performance is compared with performance of bubble sort. We found that merge sort on FPGA is 2 or more times faster than bubble sort on FPGA.