Binary Classification using K-Nearest Neighbor Algorithm on FPGA

The K-Nearest Neighbor (K-NN) algorithm is one of the most widely used algorithms for machine learning applications. Using K-NN algorithm on massively large data requires high computation power. This high computation demand can not be met by traditional software-based approach using CPUs. Field Programmable Gate Array (FPGA) can be used to implement K-NN algorithm to achieve hardware acceleration. In this paper, we implemented K-NN on Xilinx FPGA using Verilog Hardware Description Language (HDL) by exploiting the raw hardware power. The result shows that our FPGA-based solution is on average 30 thousand times faster than traditional software-based solution on CPU.