Design of Efficient Pruning Architecture for FFT Algorithm

Fast Fourier Transform (FFT) is a Digital Signal Processing (DSP) technique to compute Discrete Fourier Transform (DFT) in a faster way by utilizing the properties of the twiddle factor. Conventional FFT has a problem of computational inefficiency when the number of zero valued inputs out-numbers the number of non-zero valued inputs. This is because of the redundant computations on the zero valued inputs. This issue can be resolved by using a technique called pruning in FFT. In this paper we propose an efficient algorithm to reduce the redundant computations in FFT which improves the speed and reduces the power consumption. The proposed algorithm is implemented using verilog HDL.