A Reconfigurable Balun-LNA and Tunable Filter With Frequency-Optimized Harmonic Rejection for Sub-GHz and 2.4 GHz IoT Receivers

A CMOS reconfigurable balun-LNA and tunable filter is proposed for sub-GHz and 2.4 GHz IoT applications. The core of the LNA gain stage is composed of two cascaded inverters for the single-to-differential conversion, and the additional inverter is placed in the feedback path for the implementation of the active feedback. In the sub-GHz band, it operates as an active feedback LNA by enabling all inverter stages. At the narrow 2.4 GHz band, it operates as an inductive source degenerated LNA (ISDLNA) with a minimum noise figure (NF) by disabling the inverter in the feedback path. In order to suppress the unwanted local oscillator (LO) harmonic mixing in the sub-GHz band and provide the frequency-optimized harmonic rejection ratio (HRR), a reconfigurable Sallen-Key (SK) filter-based
$4^{\mathbf {th}}$
-order tunable filter is proposed on the basis of the modified super source follower (SSF) with enhanced loop gain. It covers the entire VHF band with a smaller capacitance tuning ratio by switching the polarity of the output of the modified SSF. Compared to previous works, this work provides the largest tuning range from 50 MHz to 700 MHz without splitting individually optimized circuits corresponding to each frequency band and using no external board components. This is the first suggestion of a fully integrated SK filter-based tunable filter to cover VHF/UHF bands through a hardware re-configurability without increasing the tuning ratio of the switched capacitor array, while providing an optimum HRR performance for corresponding operating frequencies in conjunction with harmonic rejection mixer (HRM). In addition, it proposes a hardware efficient re-configurable balun-LNA to operate as a wideband feedback LNA at sub-GHz and a narrowband ISDLNA at 2.4 GHz without the use of external input matching circuits. In the measurement, the proposed front-end achieves an average power gain (
$\text{S}_{{21}}$
) of 25.9 dB, NF of < 4.25 dB, and in-band input-referred third-order intercept point (IIP3) of
$>\!\!\!-12.8$
dBm over the tuning range from 50 MHz to 700MHz. The proposed tunable filter shows the frequency-optimized HRR from 10 dBc to 26 dBc over the tuning range while greatly reducing a silicon area. At 2.4 GHz band, it shows
$\text{S}_{{21}}$
of 14.7 dB, NF of 3.2 dB, and in-band IIP3 of −4.5 dBm. The die area of the proposed circuit, excluding I/O PADs and the measurement output buffer, is less than 2.0 mm
²
. The power consumption of the front-end working at sub-GHz and 2.4 GHz bands is 33.6 mW and 5.1 mW respectively.