THx2 Programmable Logic Block Architecture for Clockless Asynchronous FPGAs

To address some of the challenges of asynchronous design, we propose a new, decomposable asynchronous logic block architecture based on our TH $x2$ programmable threshold cell, and we use it to implement common threshold functions found in asynchronous, null convention logic circuits. At a minimum, programmable gate arrays require a programmable logic cell that can implement a complete set of logic. It is well known that a NAND function forms a complete set of logic, and in null convention logic, the TH12 and TH22 threshold cells are used to form a basic two-input NAND function. The TH $x2$ threshold cell is capable of performing both TH12 and TH22 operations, so it too forms a complete set of logic. In this paper, we present our eight-transistor mask-programmable gate array logic cell, 16-transistor field-programmable gate array logic cell, and new decomposable field-programmable gate array logic block architecture, all based on the TH $x2$ threshold cell and suitable for implementing null convention logic asynchronous functions. To minimize the TH $x2$ threshold cell area for both TH12 and TH22 modes, we designed a layout with common Euler paths and no diffusion breaks for both modes. The highly compact nature of the TH $x2$ threshold cell–along with the symmetry of the mask- and field-programmable gate array logic cells–made it an ideal candidate for an asynchronous field-programmable logic block structure. This paper is part of an ongoing project, and it only addresses the programmable logic block architecture, not a complete FPGA fabric.