A Smart SRAM-Cell Array for the Experimental Study of Variability Phenomena in CMOS Technologies

Time-Dependent Variability phenomena can have a considerable impact on circuit performance, especially for deeply-scaled technologies. To account for this, these phenomena need to be characterized and modelled. Such characterization is often performed at the device level first. Then, the model extracted from such characterization should be validated at the circuit level. To this end, this paper presents a novel chip fabricated in a 65-nm technology that contains an array of 6T SRAM cells. This chip includes some features that make it especially adequate for the characterization of the impact of Time-Dependent Variability phenomena. To demonstrate this adequacy, different tests have been performed to evaluate how Time-Dependent Variability phenomena impact several relevant performance metrics of SRAM cells.