System-Level Simulation of Electromigration in a 3 nm CMOS Power Delivery Network: The Effect of Grid Redundancy, Metallization Stack and Standard-Cell Currents

A physics-based system-level electromigration (EM) modelling platform is employed to simulate EM and its impact on the IR drop from the supply voltage to the standard-cells for a power delivery network design in a 3 nm logic node. The simulated PDN elicited high EM-tolerance. Despite EM voiding in multiple PDN segments, the EM induced IR-drop increase at the standard-cell level stayed below 3.3% without any catastrophic standard-cell failures. Use of ruthenium rails reduced IR-drop penalty of system EM by a factor of ~0.6 compared with copper rails.