Elucidation of the Density of States for Polycrystalline Silicon Vertical Thin-Film Transistors

The polycrystalline silicon vertical thin-film transistors (TFTs) with different active layer thicknesses of 150 and 300 nm were fabricated by a five-mask process and electrically characterized. The vertical TFT with 150-nm active layer thickness shows comprehensive advantages over its counterpart with 300-nm active layer, especially with a higher ON/OFF current ratio
$I_{\mathrm{ON}}/I_{\mathrm{OFF}}$
of more than 10
⁶
and higher field-effect mobility, excluding the access resistance effect. The electrical parameters were analyzed by the density of states (DOS) calculation, and smaller DOS is deduced for the device with 150-nm active layer for the same energy level. The detailed elucidation of the DOS was analyzed by introducing the intrinsic mobility and the grain boundary barrier height at the flat-band state, which gives the detailed expressions for the DOS. Polycrystalline silicon lateral TFT was also introduced to verify this evaluation method.